1. Field of the Invention
The present invention relates to a semiconductor device including a dummy pattern.
2. Description of the Related Art
Some semiconductor devices have circuit patterns of components, such as gate electrodes of transistors, wiring resistances or diffusion resistances, that are disposed at regular intervals. In formation of such circuit patterns, the outermost pattern may result in having a different shape from those of the inner patterns. This attributes to the following reason.
The outermost pattern has no pattern provided outside itself, while the other patterns each have another pattern both outside and inside itself. In the case of patterns formed by etching, for example, neighboring patterns affect determination of the shape of each pattern. For this reason, influence of neighboring patterns on the outermost pattern is different from that on the other patterns, which makes the shape of the outermost pattern different from the inner patterns. Thus, the circuit patterns end up with variation in shape. It is commonly known that such variation σ can be expressed by the following expression (1):σ∝1/√(w×t)  (1),where w denotes the width of the circuit pattern, and t denotes the height of the circuit pattern, as described in Marcel J. M. Pelgrom et al.: Matching Properties of MOS Transistors, in IEEE Journal of Solid-State Circuits, vol. 24, No. 5, October 1989, pp. 1433-1440, M. Pelgrom et al.: Matching Properties of MOS Transistors, in Nuclear Instruments and Methods in Physics Research, Section A—Accelerators, Spectrometers, Detectors and Associated Equipment, pp. 624-626, August 1991, Tuinhout, H. P., Montree, A. H., Schmitz, J., Stolk P. A.: Effects of Gate Depletion and Boron Penetration on Matching of Deep Submicron CMOS Transistors, in Electron Devices Meeting 1997, Technical Digest., International, Dec. 7-10, 1997, pp. 631-634, Digital Object Identifier 10.1109/IEDM. 1997.650463, and Pelgrom, M. J. M., Tuinhout, H. P., Vertregt, M.: Transistor Matching in Analog CMOS Applications, in Electron Devices Meeting 1998, IEDM '98 Technical Digest., International, Dec. 6-9, 1998, pp. 915-918, Digital Object Identifier 10.1109/IEDM. 1998.746503.
An effective way to reduce the variation is to provide a dummy pattern outside the outermost pattern (see, for example, Japanese Patent Application Publications Nos. Hei 7-30065, Hei 2-69972, Hei 8-223042, Sho 57-128949 and Sho 62-21260).
Along with the recent advancement in miniaturization of semiconductor devices, the size of a dummy pattern for such a semiconductor device is also required to be a minimum. On the other hand, it has been considered that the width of the dummy pattern needs to be equal to that of the circuit pattern by taking account of the above expression (1). In view of these requirements, it has been concluded that the miniaturization of dummy patterns is finite.